Field-effect voltage regulator diode

ABSTRACT

A voltage regulator diode according to the present invention comprises: a semiconductor substrate (W); a highly doped source region (3) formed in the substrate (W) to adjoin one surface thereof; a highly doped drain region (D) formed in tile substrate (W) to adjoin the above-mentioned surface; a source electrode (4) held in contact with the source region (3); a shorting electrode (9) held in contact with the drain region (D); a gate insulating portion (8a) formed between the source region (3) and the drain region (4) to partly cover the above-mentioned surface of the substrate (W); and a gate electrode (10) formed to cover the gate insulating portion (8a). The gate electrode (19) is shorted to the drain region (D) through the shorting electrode (9). As a result, a channel (12) is formed in the substrate (W) to establish conduction between the source region (3) and the drain region (4) when a gate voltage not less than a predetermined threshold value is applied.

FIELD OF THE INVENTION

The present invention generally relates to a voltage regulator diode,and more specifically to a field-effect voltage regulator diode usablein place of a conventional Zener diode.

BACKGROUND ART

It is well known that a voltage regulator diode referred to as a Zenerdiode is usable for generating a standard voltage or for voltagestabilization. The Zener diode utilizes the property of a pn junctionwhich, when subjected to an inverse voltage of no less than apredetermined value, undergoes Zener breakdown (generally below 5 V) oravalanche breakdown (generally not less than 5 V) to drasticallydecrease in its internal resistance, so that voltage fluctuates onlylittle with increasing current.

A typical prior art Zener diode has such a structure as shown in FIG. 4of the accompanying drawings. The Zener diode designated by referencenumeral 100 in FIG. 4 comprises a substrate which includes a highlydoped N-type impurity diffusion layer 101 (N+ layer), and an N-typeimpurity diffusion layer 102 epitaxially formed on the N+ layer 101. AP-type impurity diffusion region 103 is annularly formed in a surfaceportion of the N-type layer 102 of the substrate, and a highly dopedP-type region 104 (P+ region) is formed at the center of the annularP-type region 103. The surface of the substrate is covered by aninsulating layer made of silicon dioxide, and at a portion of theinsulating layer corresponding to the the P+ region is formed an openingwhere an aluminum electrode 105 is formed. The insulating layer 106 iscovered by a passivation film 107.

With the above-described structure, when a voltage Vz (breakdownvoltage) beyond a predetermined value is applied between the N+ layer101 (actually an unillustrated electrode held in contact with the N+layer 101) and the aluminum electrode 105, a breakdown takes place atthe pn junction to abruptly allow current passage. The voltage Vz inthis condition fluctuates only little with increasing current and istherefore usable for voltage stabilization and etc.

However, the prior art Zener diode having the above structure still hasthe following problems.

First, with the prior art Zener diode, since the width of the depletionlayer varies depending on the dopant concentrations on both sides of thepn junction, it is necessary to adjust the rated breakdown voltage Vz byadjusting the respective dopant concentrations in the N-type layer 102and the P+ region 104 in the course of the manufacturing process.However, since the dopant concentration in the P+ region 104 isextremely high (not less than about 10²⁰ /cm³), an attempt to accuratelyadjust the concentration by implanting a counted number of dopants willresult in an extreme cost increase. Thus, it is extremely difficult toaccurately adjust the rated breakdown voltage Vz in the course of themanufacturing process.

Secondly, the rated breakdown voltage Vz of the prior art Zener diode isto be set at a low value of about 2-3 V, the P+ region 104 must be madeto have a super high dopant concentration of about 10²¹ /cm³. Such asuper high concentration is likely to cause defects in the crystallinesubstrate, consequently leading a problem of a large leak current inaddition to difficulty of concentration adjustment.

In the third place, with the prior art Zener diode, the N-type layer 102having a relatively low dopant concentration is interposed between theN+ layer 101 and the P+ region 104, and a current flows in the N-typelayer 102 when the rated breakdown voltage Vz is applied. Though theinternal resistance decreases abruptly upon breakdown of the pnjunction, the N-type layer 102 having a relatively low dopant densitystill exhibits a non-negligible resistance. Therefore, the intendedvoltage retention cannot be sharply realized due to the resistance ofthe N-type layer 102 which causes a voltage increase attendant with acurrent increase.

DISCLOSURE OF THE INVENTION

It is, therefore, an object of the present invention to provide avoltage regulator diode whose rated voltage can be easily controlled inthe course of the manufacturing process.

Another object of the present invention to provide a voltage regulatordiode which is capable of restraining a leak current even if its ratedvoltage is set low.

A further object of the present invention to provide a voltage regulatordiode which provides improved voltage-current characteristics incomparison with a conventional Zener diode.

To achieve the above objects, the present invention provides a voltageregulator diode comprising: a semiconductor substrate; a highly dopedsource region formed in the substrate to adjoin one surface thereof; ahighly doped drain region formed in the substrate to adjoin said onesurface; a source electrode held in contact with the source region; ashorting electrode held in contact with the drain region; a gateinsulating portion formed between the source region and the drain regionto partly cover said one surface of the substrate; and a gate electrodeformed to cover the gate insulating portion; wherein the gate electrodeis shorted to the drain region through the shorting electrode, whereby achannel is formed in the substrate to establish conduction between thesource region and the drain region when a gate voltage not less than apredetermined threshold value is applied.

The operation and advantages of the voltage regulator diode having theabove-described structure will be specifically described later in detailon the basis of embodiments.

According to a preferred embodiment of the present invention, thesubstrate comprises a highly doped first layer, and a second layerformed on the first layer and having the type opposite to the firstlayer. The source region and the drain region are of the same type asthe first layer and formed in the second layer, and the drain regionextends to the first layer through the second layer. In this case, thedrain region may advantageously comprise a shallower first drainportion, and a deeper second drain portion extending to the first layerthrough the first drain portion.

According to another preferred embodiment of the present invention, thesubstrate comprises a single layer, and the source region and the drainregion are of the type opposite to the single layer and formed therein.In this case, the shorting electrode functions also as a drainelectrode.

Various features and advantages of the present invention will becomeapparent from the following description of embodiments given withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a voltage regulator diode according to afirst embodiment of the invention;

FIG. 2 is a sectional view of a voltage regulator diode according to thesecond embodiment of the invention;

FIG. 3 is a graphical chart representing the voltage-currentcharacteristics generated by the voltage regulator diode according tothe invention; and

FIG. 4 is a sectional view showing a prior art voltage regulator diode.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to FIGS. 1 through 3, preferred embodiments of the inventionare described below.

FIG. 1 shows a voltage regulator diode Z1 according to a firstembodiment of the invention. The diode Z1 comprises a semiconductorsubstrate W obtained by epitaxially forming a P-type impurity diffusionlayer 2 on a highly doped N-type layer (N+ layer) 1.

A highly doped N-type source region (N+ source region) 3 is form in anannular arrangement within the P-type layer 2 of the semiconductorsubstrate W. The N+ source region 3 is held in contact with an annularsource electrode 4 formed on the surface of the substrate W. The sourceelectrode 4 is held in ohmic contact with the P-type layer 2 via ahighly doped P-type region (P+ region) 5 extending into the P-type layer2 of the substrate W through the source region 3. Because of thisarrangement, the source electrode 4 is always held substantially at thesame potential as the P-type layer 2.

Furthermore, a highly doped N-type drain region (N+ drain region) D isformed in the P-type layer 2 of the semiconductor substrate Wsubstantially at the center of the annular source regions 3. Accordingto the first embodiment shown in FIG. 1, the drain region D comprises ashallower first drain portion 6 and a deeper second drain portion 7extending to the N+ layer 1 of the substrate W through the first drainportion 6. The reason for constituting the drain region D by the twoportions 6 and 7 will be described later.

An insulating layer 8 is formed on the surface of the semiconductorsubstrate W. At a portion of the insulating layer 8 corresponding to thesource region 8 is formed an opening where the source electrode 4 isformed. Likewise, at another portion of the insulating layer 8corresponding to the drain region D is also formed an opening where theshorting electrode 9 is formed.

The insulating layer 8 includes a gate insulating portion 8a between thesource region 8 and the drain region D. A gate electrode 10 is formed tocover the gate insulating portion 8a. According to the presentinvention, the gate electrode 10 is held in ohmic contact with theshorting electrode 9. In consequence, the gate electrode 10 is shortedto the drain region D via the shorting electrode 9 and thereby heldsubstantially at the same potential as the drain region D. In the firstembodiment, although the shorting electrode 9 is held in direct contactwith the drain region D, it does not function as a drain electrode.

In the present invention, the source electrode 4 and the shortingelectrode 9 may be preferably formed of aluminum, whereas the gateelectrode 10 may be preferably formed of polycrystalline silicon dopedwith impurities. Further, the insulating layer 8 may be preferably madeof silicon dioxide (SiO₂) for stabilizing its physical characteristics.However, the use of the above-mentioned materials is not essential, andother materials may also be used as well. Indicated by reference numeral11 in FIG. 1 is a passivation film.

In use, the voltage regulator diode Z1 is bonded such that the N+ layer1 of the substrate W is brought into contact with a pad-form drainelectrode (not shown) formed on a circuit board for example. In thiscondition, a predetermined voltage Vz is applied between the sourceelectrode 4 and the drain electrode (i.e., the N+ layer 1). In the firstembodiment, the voltage Vz is applied so that the source electrode 4becomes negative potential while the N+ layer 1 becomes positive.

As described previously, the second drain portion 7 of the N+ drainregion D extends the N+ layer 1, whereas the gate electrode 10 isshorted to the N+ drain region D via the shorting electrode 9. Thus, theN+ layer 1 and the gate electrodes 10 are held substantially at the samepotential through the drain region D and the shorting electrode 9, sothat the voltage Vz between the source electrodes 4 and the N+ layer 1can be considered as equivalent to the voltage (gate voltage) betweenthe source electrode 4 and the gate electrode 10. Imaginery lines VL inFIG. 1 show that the shorting electrode 9 and the gate electrode 10 aresubjected to the same potential as the N+ layer 1.

When the gate voltage Vz is thus applied, the field effect provided bythe gate electrode held at the positive potential attracts electrons inthe P-type layer 2 of the substrate W while repelling positive holes.However, as long as the gate voltage Vz is below a predeterminedthreshold value, the number of electrons attracted to the gate electrode10 still remains small, so that the inherent resistance of the P-typelayer 2 prevails to prevent current passage between the source region 3and the drain region D due to non-conduction.

On the other hand, when the gate voltage Vz reaches the predeterminedthreshold value, the number of electrons attracted by the gate electrode10 increases sufficiently to form a channel (N-channel) 12 right belowthe gate electrode 10. As a result, the source region 3 conducts withthe drain region D via the N-channel 12, and as indicated by arrows CFin FIG. 1, current flows along a passagethrough the N+ layer 1, thedrain region D, the N-channel 12, and the source region 3.

Once the N-channel 12 is formed, the gate voltage Vz fluctuates onlylittle even if the current increases. This is because the N+ layer 1, N+drain region D, N-channel 12, and N+ source region 3 contained in thecurrent path are equally high in electron density to render theresistance of the current path extremely low. In consequence, thethreshold voltage Vz can be held substantially constant, so that thevoltage regulator diode Z1 according to the present invention can beused in place of a conventional Zener diode.

FIG. 3 is a graph showing that the voltage regulator diode Z1 accordingto the present invention is superior to a conventional Zener diode interms of the voltage-current characteristics. The abscissa in FIG. 3represents the gate voltage Vz, whereas the ordinate represents thecurrent Iz in logarithm.

The curve A shown in the graph of FIG. 3 designates the voltage-currentcharacteristics of the inventive voltage regulator diode Z1, whereas theother curve B represents the voltage-current characteristics of aconventional Zener diode (see FIG. 4). It is evident from the graph thatthe inventive voltage regulator diode Z1 exhibits a sharp rise of thecurrent close to the threshold value of the gate voltage Vz (curve A),showing superiority in the ability of holding a constant voltage incomparison with the conventional Zener diode (curve B). This differenceis based on the fact that, after achieving a predetermined voltage, theinventive voltage regulator diode Z1 allows the current to flow throughthe N-channel 12 having an extremely low resistance, whereas the priorart Zener diode 100 (FIG. 4) makes the current to flow through theN-type layer 102 which still has a relatively high resistance.

In the inventive voltage regulator diode Z1, the threshold gate voltagevalue Vz (corresponding to the breakdown voltage of a conventional Zenerdiode) can properly be adjusted by varying any of the following threeparameters (factors).

(1) Thickness of the gate insulating portion 8a

(2) Concentration of impurities (dopants) in the P-type layer 2

(3) Length of the N-channel 12

The thickness of the gate insulating portion 8a, which affects the theability of the gate electrode 10 to attract electrons in the P-typelayer 2, can be utilized for controlling the threshold gate voltage Vz.

Since thickness of the gate insulating portion 8a can easily andstrictly be adjusted in the course of or after forming the insulatinglayer 8, this parameter can be utilized for conveniently adjusting thethreshold gate voltage value Vz.

The concentration of the dopants (the above factor (2)) in the P-typelayer 2 determines the ability of supplying electrons to the N-channel12 and therefore can be utilized to control the threshold gate voltageVz. Since this dopant concentration need not be set high, a countednumber of dopants may be implanted without much increasing theproduction cost. Thus, the control of the threshold gate voltage Vz canbe easily and strictly performed by adjusting this parameter.

The length of the N-channel 12 (the above factor (3)) is equal to thedistance between the N+ source region 3 and the N+ drain region D.Therefore, by performing dopant diffusion simultaneously with respect toboth the source region 8 and the first drain portion 6 of the drainregion D, it is possible to easily and strictly control the length ofthe N-channel 12, i.e., the threshold gate voltage Vz.

Any of the above-mentioned parameters (1)-(3) has nothing to do with thedopant concentration in the source region 3 and the drain region D. Thisis because it is only the presence or absence of the channel 12 that itimportant for the operation of the inventive voltage reulator diode Z1,so that the source region 3 and the drain region D need only be doped ata high concentration (not super high concentration). Accordingly, thethreshold gate voltage Vz can be easily controlled with a relativelyhigh degree of freedom by conveninently adjusting any of the aboveparameters (1)-(3). Further, even when setting at a low voltage of 2-3V, it is unnecessary to dope the source region 3 and the drain region Dat a super high concentration (e.g. 10²¹ /cm³), so that the problem ofleak current encountered in a conventional Zener diode can be avoided.

As already described, the N+ drain region D comprises the shallowerfirst drain portion 6 and the deeper second drain portion 7 whichextends through the first drain portion into contact with the N+layer 1. The reason for such a structure for the N+ drain region D isclosely related to the above-mentioned parameter (3), as describedbelow.

For facilitating adjustment of the distance between the source region 3and the drain region D, namely the length of the N-channel 12, it isnecessary to perform dopant diffusion simultaneously with respect toboth the source region 3 and the drain region D, and it is preferablethat the dopant diffusion be relatively shallow. On the other hand, thesource region 3 must not extend to the N+ layer 1, whereas the drainregion D must extend to the N+ layer 1. Thus, the whole drain region Dand the source region 3 cannot be formed simultaneously. In view ofthis, the drain region D is divided into the first drain portion 6 andthe second drain portion 7, whereby the first drain portion 6 is formedsimultaneously with the source region, and the second drain portion 7 isthereafter formed by a diffusion method having a high degree of dopantpenetration.

FIG. 2 shows a voltage regulator diode Z2 according to second embodimentof the present invention. The voltage regulator diode Z2 comprises asemiconductor substrate W' solely consisting of a P-type impuritydiffusion layer 2', thus being advantageously more economical than thefirst embodiment which utilizes the epitaxially formed substrate W.

A highly doped N-type source region (N+ source region) 3' is formed inthe P-type layer 2' generally at the center of the substrate W'. The N+source region 3' is held in contact with a source electrode 4' formed onthe surface of the substrate W'. The source electrode 4' is held inohmic contact with the P-type layer 2' via a highly doped P-type region(P+ region) 5' extending into the interior of the P-type layer 2'through the N+ source region 3'. Because of such an arrangement, thesource electrode 4' is always held substantially at the same potentialas the P-type layer 2'.

Further, a highly doped N-type drain regions (N+ drain region) D' isannularly formed in the P-type layer 2' around the center N+ sourceregion 3'. In contrast to the first embodiment shown in FIG. 1, the N+drain region D' solely comprises a relatively shallow drain portion 6'.

The reason for this is that the semiconductor substrate W' is devoid ofan N+ layer.

An insulating layer 8' is formed on the surface of the semiconductorsubstrate W' (i.e., the P-type layer 2'). At a portion of the insulatinglayer 8' corresponding to the N+ source region 3' is formed an openingwhere the source electrode 4' is formed. At another portion of theinsulating layer 8' corresponding to the N+ drain regions D' is alsoformed an opening where a shorting electrode 9' functioning also as adrain electrode is formed.

On the other hand, the insulating layer 8' has a gate insulating portion8a' between the N+ source region 3' and the N+ drain region D', and agate electrode 10' is formed to cover the gate insulating portion 8a'.According to the present invention, the gate electrode 10' is held inohmic contact with the shorting electrode 9'. As a result, the gateelectrode 10' is shorted to the N+ drain region D' via the shortingelectrode 9', whereby these three parts are held substantially at anequal potential.

The materials for the source electrode 4', short-circuiting electrode9', gate electrode 10' and insulating layer 8' of the second embodimentcan be selected in the same manner as in the first embodiment. Referencenumeral 11' in FIG. 2 designates a passivation film.

In operation, a predetermined voltage Vz is applied between the sourceelectrode 4' and the shorting electrode 9' functioning as a drainelectrode. The polarity of the voltage Vz is such that the sourceelectrode 4' is negative, whereas the shorting electrodes 9' ispositive.

As previously described, the gate electrode 10' is held in ohmic contactwith the shorting electrode 9'. Therefore, the voltage Vz between thesource electrode 4' and the shorting electrode 9' can be considered asequivalent to the voltage (gate voltage) between the source electrode 4'and the gate electrode 10'. An imaginery line VL' in FIG. 2 representsthat the shorting electrode 9' and the gate electrode 10' are held atthe same potential.

When the gate voltage Vz is thus applied, the field effect of thepositively charged gate electrode 10' attracts electrons contained inthe P-type layer 2' while repelling positive holes. Therefore, when thegate voltage Vz exceeds a predetermined threshold value, a channel(N-channel) 12' is formed right below the gate electrode 10'. Thus, thevoltage regulator diode Z2 of the second embodiment has the sameoperation and advantages as that of the first embodiment. However, adifference from the first embodiment resides in that current passes onlyalong the surface of the semiconductor substrate W'.

According to either of the embodiments described above, the N-channel 12(or 12') is formed. However, a P-channel may be formed if the P-typeelements are replaced by N-type elements while replacing the N-typeelements by P-type elements. It should be understood that thesemodifications are included in the scope of the present invention.

INDUSTRIAL UTILITY

A voltage regulator diode according to the present invention can beincorporated in a standard voltage generating circuit or a voltagestabilizing circuit as a substitute for a conventional Zener diode. Inparticular, it is expected that the inventive voltage regulator diode isuseful where a low rated voltage of 2-3 V is required.

We claim:
 1. A voltage regulator diode comprising: a semiconductorsubstrate including at least a head side semiconductor layer of a firsttype; a source region formed in the head side semiconductor layer toadjoin a surface thereof and highly doped to be of a second typeopposite to the first type; a highly doped drain region of the secondtype formed in the head side semiconductor layer to adjoin said surface;a source electrode held in contact with the source region; a shortingelectrode held in contact with the drain region; a gate insulatingportion formed between the source region and the drain region to partlycover said surface of the head side semiconductor layer; and a gateelectrode formed to cover the gate insulating portion; wherein the gateelectrode is shorted to the drain region through the shorting electrode,whereby a channel is partially formed in the head side semiconductorlayer to establish conduction between the source region and the drainregion when a gate voltage not less than a predetermined threshold valueis applied,wherein the substrate comprises a highly doped tail sidesemiconductor layer of the second type in addition to the head sidesemiconductor layer of the first type, the drain region extending to thetail side semiconductor layer through the head side semiconductor layer.2. The voltage regulator diode according to claim 1, wherein the drainregion comprises a shallower first drain portion, and a deeper seconddrain portion extending to the tail side semiconductor layer through thefirst drain portion.
 3. The voltage regulator diode according to claim1, wherein the gate insulating portion is made of silicon dioxide. 4.The voltage regulator diode according to claim 1, wherein the gateelectrode is made of polycrystalline silicon.
 5. The voltage regulatordiode according to claim 1, wherein the source electrode and theshorting electrode are made of aluminum.